A biCMOS device may have high speed, low power consumption, and high integration. A biCMOS device is a device (e.g. a chip) that includes both a bipolar transistor and a CMOS transistor. A biCMOS device may have low-power consumption characteristics and high-integration characteristics of CMOS transistors and high-speed switching characteristics and a high-current driving capabilities of bipolar transistors.
There is a variety of bipolar transistor manufacturing methods suitable for the biCMOS technology. These methods may be optimized to be compatible with CMOS transistor manufacturing methods, while maintaining high-speed switching characteristics and high-current driving capabilities. It may be desirable to integrate a Polysilicon/Insulator/Polysilicon (PIP) capacitor on a biCMOS device adjacent to a bipolar transistor. Integrating both a bipolar transistor and a PIP capacitor on a biCMOS device may be accomplished by a high-integration technique.
Example FIGS. 1A to 1D are cross-sectional views illustrating a method of manufacturing a biCMOS device having a bipolar transistor and a PIP capacitor. As illustrated in FIG. 1A, P-type semiconductor substrate 10 may include PIP capacitor region A and bipolar transistor region B. Semiconductor substrate 10 may include buried layer 12 (e.g. doped with an N-type material) formed in bipolar transistor region B. An epitaxial layer (not shown) may be formed on buried layer 12. First well region 14a (e.g. doped with N-type material) and second well region 14b (e.g. doped with P-type material) may be formed adjacent to each other within a epitaxial layer (not shown).
Field insulating layer 16 may be formed over surfaces of PIP capacitor region A and bipolar transistor region B. First polysilicon layer 18 may be formed over field insulating layer 16. A photoresist layer (not shown) may be formed over first polysilicon layer 18. Mask pattern 19 (e.g. for ion implantation) may be formed from a photoresist layer.
As illustrated in FIG. 1B, an ion implantation process using the mask pattern 19 may be performed by implanting ions into exposed areas of first polysilicon layer 18 to form doped first polysilicon layer 18a. As illustrated in FIG. 1C, mask pattern 19 may be stripped. First polysilicon layer 18 may be patterned so that only doped first polysilicon layer 18a remains. First polysilicon layer 18a may become a lower electrode of a PIP capacitor. Capacitor dielectric layer 20 and upper electrode 22 may be sequentially formed on doped first polysilicon layer 18a. 
As illustrated in FIG. 1D, collector region 28 may be formed by doping a region of first well region 14a with N-type material. Emitter region 26 may be formed by doping a region of second well region 14b with N-type material. Base region 24 may be formed by doping a region of second well region 14b with P-type material. Base region 24 and emitter region 26 may be isolated from each other. Buried layer 12 and first well region 14a may work with collector region 28 in a bipolar transistor. Second well region 14b may work with base region 24.
A biCMOS device (e.g. a chip including a CMOS transistor and a bipolar transistor) may include the structure illustrated in FIGS. 1A through 1D. The concentration of N-type material in first well region 14a may be relatively low compared to a device that does not integrate CMOS transistors with bipolar transistors. Accordingly, it may be difficult to form a bipolar transistor having an adequate high amplification rate if the series resistance of collector region 28 is relatively high.